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STHVDAC-253M

Register table

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4.2

RFFE interface, command and data frame structure

The STHVDAC-253M RFFE interface has been implemented to support the following

command sequences:

•

Register WRITE

•

Register READ

•

Extended Register Write

These supported command sequences are described in Table 13.

All frames are required to end with a single parity bit. The parity bit shall be driven such that

the total number of bits in the frame that are driven to logic level 1, including the parity bit, is

odd. In case the device detects a parity error, the frame is considered not valid and is

ignored.

Table 13. Support command sequences

SSC

(1)

Command frame

Data frame

Register

write

01 0

USID

(2)

0 1 0

Reg adress [4,0]

P

(3)

DATA[7,0]

P

BP

(4)

Register

read

0 1 0 USID 0 1 1

Reg adress [4,0]

P

BP

DATA

[7,0]

PBP

Extended

register

write

01 0 USID 0 0 0 0

00

0

0

P Adress[7,0]

P

Up to 4 bytes of data with parity BP

11

1

1

1. Sequence start condition

2. Unique slave identifier

3. Parity bit

4. Bus park cycle

5. Byte count