DocID025735 Rev 1

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STHVDAC-253M

Theory of operation

27

3.8

Power-up / down sequence

Table 7

and Figure 4 describe the HVDAC settling time requirements and recommended

timing diagrams.

Switching from shutdown to active mode is triggered by setting VIO to high level.

Switching from active to low power mode will occur by setting PWR_MODE bits to 10b in

register 28.

Switching from low power to active mode will occur by setting power mode bits to 01b in

register 28

Following active mode command (from Shutdown or from Low power), the HVDAC will be

HVDAC output voltages will vary from the initial to the updated DAC command.

Figure 4. Power up and low power sequence

3.9

Power supply sequencing

the first ON.

VIO should then be switched as described in previous sections.

DAC

Low power

DAC

Active

Shut down

Active

Low power

Active

Shut

down

Active

VBATT

VIO

MIPI_CLK_DATA

V HV

VOUT