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DS2148 bảng dữ liệu(PDF) 38 Page - Dallas Semiconductor |
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DS2148 bảng dữ liệu(HTML) 38 Page - Dallas Semiconductor |
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38 / 75 page ![]() DS2148/Q48 38 of 75 RIR1 (08H): RECEIVE INFORMATION REGISTER 1 (MSB) (LSB) ZD 16ZD HBD RCLC RUA1C JALT N/A N/A SYMBOL POSITION DESCRIPTION ZD (latched) RIR1.7 Zero Detect. Set when a string of at least four (ETS = 0) or eight (ETS = 1) consecutive zeros (regardless of the length of the string) have been received. Will be cleared when read. 16ZD (latched) RIR1.6 Sixteen Zero Detect. Set when at least 16 consecutive zeros (regardless of the length of the string) have been received. Will be cleared when read. HBD (latched) RIR1.5 HDB3/B8ZS Word Detect. Set when an HDB3 (ETS = 0) or B8ZS (ETS = 1) code word is detected independent of whether the receive HDB3/B8ZS mode (CCR4.6) is enabled. Will be cleared when read. Useful for automatically setting the line coding. RCLC (latched) RIR1.4 Receive Carrier Loss Clear. Set when the RCL alarm has met the clear criteria defined in Table 7-1. Will be cleared when read. RUA1C (latched) RIR1.3 Receive Unframed All Ones Clear. Set when the unframed all ones signal is no longer detected. Will be cleared when read. See Table 7-1. JALT (latched) RIR1.2 Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4 bits of its useful limit. Will be cleared when read. Useful for debugging jitter attenuation operation. N/A RIR1.1 Not Assigned. Could be any value when read. N/A RIR1.0 Not Assigned. Could be any value when read. |
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