STM32L432KB datasheet(49/149 Pages) STMICROELECTRONICS

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STM32L432KB STM3L432KC

Pinouts and pin description

PA14

(JTCK-

SWCLK)

I/O

(3)

JTCK-SWCLK, LPTIM1_OUT,

I2C1_SMBA, SWPMI1_RX,

SAI1_FS_B, EVENTOUT

PA15

(JTDI)

I/O

(3)

JTDI, TIM2_CH1, TIM2_ETR,

USART2_RX, SPI1_NSS,

SPI3_NSS,

USART3_RTS_DE,

TSC_G3_IO1,

SWPMI1_SUSPEND,

EVENTOUT

PB3

(JTDO-

TRACE

SWO)

I/O

FT_a (3)

JTDO-TRACESWO,

TIM2_CH2, SPI1_SCK,

SPI3_SCK,

USART1_RTS_DE,

SAI1_SCK_B, EVENTOUT

COMP2_INM

PB4

(NJTRST)

I/O

FT_fa (3)

NJTRST, I2C3_SDA,

SPI1_MISO, SPI3_MISO,

USART1_CTS, TSC_G2_IO1,

SAI1_MCLK_B, EVENTOUT

COMP2_INP

PB5

I/O

LPTIM1_IN1, I2C1_SMBA,

SPI1_MOSI, SPI3_MOSI,

USART1_CK, TSC_G2_IO2,

COMP2_OUT, SAI1_SD_B,

TIM16_BKIN, EVENTOUT

PB6

I/O

FT_fa

LPTIM1_ETR, I2C1_SCL,

USART1_TX, TSC_G2_IO3,

SAI1_FS_B, TIM16_CH1N,

EVENTOUT

COMP2_INP

PB7

I/O

FT_fa

LPTIM1_IN2, I2C1_SDA,

USART1_RX, TSC_G2_IO4,

EVENTOUT

COMP2_INM, PVD_IN

PH3/

BOOT0

I/O

EVENTOUT

BOOT0

VSS

1VDD

1. PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of

current (3 mA), the use of GPIOs PC14 to PC15 in output mode is limited:

- The speed should not exceed 2 MHz with a maximum load of 30 pF

- These GPIOs must not be used as current sources (e.g. to drive an LED).

2. After a Backup domain power-up, PC14 and PC15 operate as GPIOs. Their function then depends on the

content of the RTC registers which are not reset by the system reset. For details on how to manage these

GPIOs, refer to the Backup domain and RTC register descriptions in the RM0393 reference manual.

3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on

PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

Table 13. STM32L432xx pin definitions (continued)

Number

Pin functions

Alternate functions

Additional functions

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