STM32L432KB datasheet(23/149 Pages) STMICROELECTRONICS

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STM32L432KB STM3L432KC

Functional overview

3.9.5

Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is

“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is

deactivated when the reset source is internal.

3.10

Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous

communication between peripherals, saving CPU resources thus power supply

consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run

and sleep, Stop 0, Stop 1 and Stop 2 modes.

1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not

available.

2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.

3. The SRAM clock can be gated on or off.

4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.

5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16

is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put

off when the peripheral does not need it anymore.

6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start,

address match or received frame event.

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address

match.

8. Voltage scaling Range 1 only.

9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PA2.

11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is

lost when exiting the Shutdown mode.

Table 4. STM32L432xx peripherals interconnect matrix

Interconnect source

Interconnect

destination

Interconnect action

TIMx

Timers synchronization or chaining

ADCx

DACx

Conversion triggers

DMA

Memory to memory transfer trigger

COMPx

Comparator output blanking

TIM15/TIM16

IRTIM

Infrared interface output generation

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