STM32L432KB datasheet(43/149 Pages) STMICROELECTRONICS

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DocID028798 Rev 2

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STM32L432KB STM3L432KC

Functional overview

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Transmission

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Three transmit mailboxes

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Configurable transmit priority

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Reception

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Two receive FIFOs with three stages

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14 Scalable filter banks

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Identifier list feature

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Configurable FIFO overrun

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Time-triggered communication option

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Disable automatic retransmission mode

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16-bit free running timer

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Time Stamp sent in last two data bytes

•

Management

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Maskable interrupts

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Software-efficient mailbox mapping at a unique address space

3.30

Universal serial bus (USB)

The STM32L432xx devices embed a full-speed USB device peripheral compliant with the

USB specification version 2.0. The internal USB PHY supports USB FS signaling,

embedded DP pull-up and also battery charging detection according to Battery Charging

Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function

interface with added support for USB 2.0 Link Power Management. It has software-

configurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.

It requires a precise 48 MHz clock which can be generated from the internal main PLL or by

the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this

oscillator can be taken from the USB data stream itself (SOF signalization) which allows

crystal less operation.

3.31

Clock recovery system (CRS)

The STM32L432xx devices embed a special block which allows automatic trimming of the

internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device

operational range. This automatic trimming is based on the external synchronization signal,

which could be either derived from USB SOF signalization, from LSE oscillator, from an

external signal on CRS_SYNC pin or generated by user software. For faster lock-in during

startup it is also possible to combine automatic trimming with manual trimming action.

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