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STM32L100RC bảng dữ liệu(PDF) 45 Page - STMicroelectronics |
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STM32L100RC bảng dữ liệu(HTML) 45 Page - STMicroelectronics |
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45 / 104 page ![]() DocID024995 Rev 4 45/104 STM32L100RC 96 6.3.2 Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the conditions summarized in Table 12. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up . 3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled. 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 63: Thermal characteristics on page 100). 5. In low-power dissipation state, TA can be extended to -40°C to 105°C temperature range as long as TJ does not exceed TJ max (see Table 63: Thermal characteristics on page 100). Table 13. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit tVDD(1) VDD rise time rate BOR detector enabled 0 - ∞ µs/V BOR detector disabled 0 - 1000 VDD fall time rate BOR detector enabled 20 - ∞ BOR detector disabled 0 - 1000 TRSTTEMPO(1) Reset temporization VDD rising, BOR enabled - 2 3.3 ms VDD rising, BOR disabled(2) 0.4 0.7 1.6 VPOR/PDR Power on/power down reset threshold Falling edge 1 1.5 1.65 V Rising edge 1.3 1.5 1.65 VBOR0 Brown-out reset threshold 0 Falling edge 1.67 1.7 1.74 Rising edge 1.69 1.76 1.8 VBOR1 Brown-out reset threshold 1 Falling edge 1.87 1.93 1.97 Rising edge 1.96 2.03 2.07 VBOR2 Brown-out reset threshold 2 Falling edge 2.22 2.30 2.35 Rising edge 2.31 2.41 2.44 |
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