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Instruction set

Doc ID 13770 Rev 3

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Instruction set

18.1

CPU addressing modes

The CPU features 17 different addressing modes which can be classified in seven main

groups as listed in the following table:

The CPU instruction set is designed to minimize the number of bytes required per

instruction: To do so, most of the addressing modes may be divided in two submodes called

long and short:

●

Long addressing mode is more powerful because it can use the full 64 Kbyte address

space; however, it uses more bytes and more CPU cycles.

●

Short addressing mode is less powerful because it can generally only access page

zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All

memory to memory instructions use short addressing modes only (CLR, CPL, NEG,

BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP).

The ST7 Assembler optimizes the use of long and short addressing modes.

Table 97.

Addressing modes

Group

Example

Inherent

NOP

Immediate

LD A,#$55

Direct

LD A,$55

Indexed

LD A,($55,X)

Indirect

LD A,([$55],X)

Relative

JRNE loop

Bit operation

BSET

byte,#5

Table 98.

CPU addressing mode overview

Mode

Syntax

Destination

Pointer

address

(Hex.)

Pointer

size

(Hex.)

Length

(bytes)

Inherent

nop

+ 0

Immediate

ld A,#$55

+ 1

Short

Direct

ld A,$10

00..FF

+ 1

Long

Direct

ld A,$1000

0000..FFFF

+ 2

No Offset

Direct

Indexed

ld A,(X)

00..FF

+ 0

Short

Direct

Indexed

ld A,($10,X)

00..1FE

+ 1

Long

Direct

Indexed

ld A,($1000,X)

0000..FFFF

+ 2

Short

Indirect

ld A,[$10]

00..FF

byte

+ 2

Long

Indirect

ld A,[$10.w]

0000..FFFF

00..FF

word

+ 2

Short

Indirect

Indexed

ld A,([$10],X)

00..1FE

00..FF

byte

+ 2

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