ST72325AR7-Auto datasheet(51/243 Pages) STMICROELECTRONICS

tên linh kiện	ST72325AR7-Auto

Giải thích chi tiết về linh kiện	SCI asynchronous serial interface

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Obsolete

Product(s)

- Obsolete

Product(s)

ST72325xxx-Auto

Supply, reset and clock management

Doc ID 13770 Rev 3

51/243

6.6.4

Low power modes

6.6.5

Interrupts

The CSS or AVD interrupt eventsgenerate an interrupt if the corresponding Enable Control

Bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM

instruction).

Figure 18.

Clock filter function

Table 12.

Effect of low power modes on SI

Mode

Effect

Wait

No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.

Halt

The SICSR register is frozen.The CSS (including the safe oscillator) is disabled until

HALT mode is exited. The previous CSS configuration resumes when the MCU is woken

up by an interrupt with “exit from HALT mode” capability or from the counter reset value

when the MCU is woken up by a RESET.

Table 13.

CSS AVD interrupt control/wake-up capability

Interrupt event

Event flag

Enable control bit

Exit from Wait

Exit from Halt

CSS event

detection (safe

oscillator

activated as main

clock)

CSSD

CSSIE

Yes

AVD event

AVDF

AVDIE

Yes

fOSC2

fCPU

fOSC2

fCPU

fSFOSC

Clock Filter Function

Clock Detection Function

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