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ST72321R7-Auto bảng dữ liệu(PDF) 212 Page - STMicroelectronics

tên linh kiện ST72321R7-Auto
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ST72321R7-Auto bảng dữ liệu(HTML) 212 Page - STMicroelectronics

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Electrical characteristics
ST72321xx-Auto
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Doc ID 13829 Rev 1
Figure 93.
SPI slave timing diagram with CPHA = 0(1)
1.
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends on the I/O port configuration.
Figure 94.
SPI slave timing diagram with CPHA = 1(1)
1.
Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its
alternate function capability released. In this case, the pin status depends of the I/O port configuration.
SS INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tv(SO)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
MSB IN
BIT6 OUT
LSB IN
LSB OUT
See note 2
CPOL=0
CPOL=1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
See
note 2
BIT1 IN
SS INPUT
CPHA=1
MOSI INPUT
MISO OUTPUT
CPHA=1
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
ta(SO)
tsu(SI)
th(SI)
MSB OUT
BIT6 OUT
LSB OUT
See
CPOL=0
CPOL=1
tsu(SS)
th(SS)
tdis(SO)
th(SO)
See
note 2
note 2
tc(SCK)
HZ
tv(SO)
MSB IN
LSB IN
BIT1 IN



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