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ST72321R7-Auto bảng dữ liệu(PDF) 57 Page - STMicroelectronics

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ST72321R7-Auto bảng dữ liệu(HTML) 57 Page - STMicroelectronics

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ST72321xx-Auto
Interrupts
Doc ID 13829 Rev 1
57/243
7.6
External interrupts
7.6.1
I/O port interrupt sensitivity
The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR
register (Figure 21). This control allows to have up to four fully independent external
interrupt source sensitivities.
Each external interrupt source can be generated on four (or five) different events on the pin:
●
Falling edge
●
Rising edge
●
Falling and rising edge
●
Falling edge and low level
●
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity bits in the EICR register can be modified
only when the I1 and I0 bits of the CC register are both set to 1 (level 3). This means that
interrupts must be disabled before changing sensitivity.
The pending interrupts are cleared by writing a different value in the ISx[1:0], IPA or IPB bits
of the EICR.



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