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ST72321R7-Auto bảng dữ liệu(PDF) 198 Page - STMicroelectronics

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ST72321R7-Auto bảng dữ liệu(HTML) 198 Page - STMicroelectronics

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Electrical characteristics
ST72321xx-Auto
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Doc ID 13829 Rev 1
19.5.5
PLL characteristics
The user must take the PLL jitter into account in the application (for example, in serial
communication or sampling of high frequency signals). The PLL jitter is a periodic effect,
which is integrated over several CPU cycles. Therefore, the longer the period of the
application signal, the less it is impacted by the PLL jitter.
Figure 81 shows the PLL jitter integrated on application signals in the range 125 kHz to
4 MHz. At frequencies of less than 125 kHz, the jitter is negligible.
Figure 81.
Integrated PLL jitter versus signal frequency(1)
1.
Measurement conditions: fCPU = 8 MHz
Table 119.
PLL characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fOSC
PLL input frequency range
2
4
MHz
 f
CPU/fCPU
Instantaneous PLL jitter(1)
1.
Data based on characterization results
fOSC = 4 MHz
1.0
2.5
%
fOSC = 2 MHz
2.5
4.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
Application Frequency
+/-Jitter (%)



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