SPC563M64L5 datasheet(10/48 Pages) STMICROELECTRONICS

10 / 48 page

Device overview

SPC563Mxx

10/48

Doc ID 13850 Rev 6

3.2

Feature list

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Operating parameters

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Fully static operation, 0 MHz – 80 MHz (plus 2% frequency modulation - 82 MHz)

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–40

°C to 150 °C junction temperature operating range

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Low power design

Less than 400 mW power dissipation (nominal)

Designed for dynamic power management of core and peripherals

Software controlled clock gating of peripherals

Low power stop mode, with all clocks stopped

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Fabricated in 90 nm process

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1.2 V internal logic

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Single power supply with 5.0 V

−10% / +5% (4.5 V to 5.25 V) with internal

regulator to provide 3.3 V and 1.2 V for the core

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Input and output pins with 5.0 V

−10% / +5% (4.5 V to 5.25 V) range

35%/65% VDDE CMOS switch levels (with hysteresis)

Selectable hysteresis

Selectable slew rate control

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Nexus pins powered by 3.3 V supply

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Designed with EMI reduction techniques

Phase-locked loop

Frequency modulation of system clock frequency

On-chip bypass capacitance

Selectable slew rate and drive strength

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High performance e200z335 core processor

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32-bit Power Architecture Book E programmer’s model

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Variable Length Encoding Enhancements

Allows Power Architecture instruction set to be optionally encoded in a mixed 16

and 32-bit instructions

Results in smaller code size

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Single issue, 32-bit Power Architecture technology compliant CPU

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In-order execution and retirement

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Precise exception handling

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Branch processing unit

Dedicated branch address calculation adder

Branch acceleration using Branch Lookahead Instruction Buffer

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Load/store unit

One-cycle load latency

Fully pipelined

Big and Little Endian support

Misaligned access support

Zero load-to-use pipeline bubbles

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Thirty-two 64-bit general purpose registers (GPRs)

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