LNBH25 datasheet(11/34 Pages) STMICROELECTRONICS

11 / 34 page

LNBH25

Pin configuration

Doc ID 022433 Rev 4

11/34

Pin configuration

Figure 5.

Pin connections (top view)

GND

DSQOUT

DSQIN/

EXTM

VUP

VCC

PGND

FLT

LX-A

SDA

ISEL

DETIN

VOUT

VBYP

BPSW

ADDR

SCL

GND

DSQOUT

DSQIN

VUP

VCC

PGND

FLT

SDA

ISEL

DETIN

VOUT

VBYP

BPSW

ADDR

SCL

AM09909v1

Table 2.

Pin description

Pin n°

Symbol

Name

Pin function

2FLT

FLT

Open drain output for IC fault conditions. It is set low in case of

overload (OLF bit) or overheating status (OTF bit) or power not good

(PNG) is detected. To be connected to pull-up resistor (5 V max.).

N-MOS drain

Integrated N-channel Power MOSFET drain.

P-GND

Power ground

DC-DC converter power ground. To be connected directly to the

Epad.

ADDR

Address setting

Two I²C bus addresses available by setting the address pin level

voltage. See

Table 16.

SCL

Serial clock

Clock from I²C BUS.

SDA

Serial data

Bi-directional data from/to I²C BUS.

ISEL

Current selection

The resistor “RSEL” connected between ISEL and GND defines the

linear regulator current limit threshold. Refer to

Section 2.6 in the

Application Information section. Also see the ISET bit description in

Table 9.

GND

Analog ground

Analog circuits ground. To be connected directly to the Epad.

BYP

Bypass capacitor

Needed for internal pre-regulator filtering. The BYP pin is intended

only to connect an external ceramic capacitor. Any connection of

this pin to external current or voltage sources may cause permanent

damage to the device.

VCC

Supply input

8 to 16 V IC DC-DC power supply.

LNBH25 bảng dữ liệu(PDF) 11 Page - STMicroelectronics

LNBH25 bảng dữ liệu(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

bảng dữ liệu tải về

Link URL