L6706 datasheet(44/47 Pages) STMICROELECTRONICS

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Layout guidelines

L6706

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Doc ID 15698 Rev 2

points far from the load will cause a non-optimum load regulation, increasing output

tolerance. Locate current reading components close to the device. The PCB traces

connecting the reading point must use dedicated nets, routed as parallel traces in order to

avoid the pick-up of any common mode noise. It's also important to avoid any offset in the

measurement and, to get a better precision, to connect the traces as close as possible to

the sensing elements. Small filtering capacitor can be added, near the controller, between

VOUT and SGND, on the CS- line to allow higher layout flexibility. Power connections and

related connections layout.

Figure 26.

Power connections and related connections layout

Note:

Boot capacitor extra charge. systems that do not use schottky diodes might show big

negative spikes on the phase pin. This spike can be limited as well as the positive spike but

has an additional consequence: it causes the bootstrap capacitor to be over-charged. This

extra-charge can cause, in the worst case condition of maximum input voltage and during

particular transients, that boot-to-phase voltage overcomes the abs. max. ratings also

causing device failures. It is then suggested in this cases to limit this extra-charge by adding

a small resistor in series to the boot diode (see Figure 26) and by using standard and low-

capacitive diodes.

20.3

Embedding L6706 - Based VR

When embedding the VRD into the application, additional care must be taken since the

whole VRD is a switching DC/DC regulator and the most common system in which it has to

work is a digital system such as MB or similar. In fact, latest MB has become faster and

powerful: high speed data bus are more and more common and switching-induced noise

produced by the VRD can affect data integrity if not following additional layout guidelines.

Few easy points must be considered mainly when routing traces in which high switching

currents flow (high switching currents cause voltage spikes across the stray inductance of

the trace causing noise that can affect the near traces):

Keep safe guarding distance between high current switching VRD traces and data buses,

especially if high-speed data bus to minimize noise coupling. Keep safe guard distance or

filter properly when routing bias traces for I/O sub-systems that must walk near the VRD.

Possible causes of noise can be located in the PHASE connection, MOSFET gate drive and

Input voltage path (from input bulk capacitors and HS drain). Also PGND connection must

be considered if not insisting on a power ground plane. These connections must be carefully

kept far away from noise-sensitive data bus. Since the generated noise is mainly due to the

switching activity of the VRM, noise emissions depend on how fast the current switches. To

reduce noise emission levels, it is also possible, in addition to the previous guidelines, to

reduce the current slope by properly tuning the HS gate resistor and the PHASE snubber

network.

CIN

VIN

UGATE

PHASE

LGATE

PGND

LOAD

BOOT

PHASE

VCC

SGND

+Vcc

CIN

VIN

LOAD

To limit C

BOOT

Extra-Charge

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