TMS320VC5416 datasheet(71/98 Pages) TI1

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5.5.6 HOLD and HOLDA Timings

TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

Table 5-15 and Table 5-16 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5-14).

Table 5-15. HOLD and HOLDA Timing Requirements

5416-120

5416-160

UNIT

MIN

MAX

tw(HOLD)

Pulse duration, HOLD low duration

4H+8

tsu(HOLD)

Setup time, HOLD before CLKOUT low(1)

(1)

This input can be driven from an asynchronous source, therefore, there are no specific timing requirments with respect to CLKOUT.

However, if this timing is met, the input will be recognized on the CLKOUT edge referenced.

Table 5-16. HOLD and HOLDA Switching Characteristics

5416-120

5416-160

PARAMETER

UNIT

MIN

MAX

tdis(CLKL-A)

Disable time, Address, PS, DS, IS high impedance from CLKOUT low

tdis(CLKL-RW)

Disable time, R/W high impedance from CLKOUT low

tdis(CLKL-S)

Disable time, MSTRB, IOSTRB high impedance from CLKOUT low

ten(CLKL-A)

Enable time, Address, PS, DS, IS valid from CLKOUT low

2H+3

ten(CLKL-RW)

Enable time, R/W enabled from CLKOUT low

2H+3

ten(CLKL-S)

Enable time, MSTRB, IOSTRB enabled from CLKOUT low

2H+3

Valid time, HOLDA low after CLKOUT low

– 1

tv(HOLDA)

Valid time, HOLDA high after CLKOUT low

– 1

tw(HOLDA)

Pulse duration, HOLDA low duration

2H–3

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