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DM8147SCIS0 bảng dữ liệu(PDF) 21 Page - Texas Instruments

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tên linh kiện DM8147SCIS0
Giải thích chi tiết về linh kiện  DaVinci Video Processors
PDF  377 Pages
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nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
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DM8147SCIS0 bảng dữ liệu(HTML) 21 Page - Texas Instruments

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TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
2.7
Media Controller Overview
The Media Controller has the responsibility of managing the HDVPSS, HDVICP2, and ISS modules.
For more details on the Media Controller, see the Media Controller Subsystem section of the Chip Level
Resources chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).
2.8
HDVICP2 Overview
The HDVICP2 is a Video Encoder/Decoder hardware accelerator supporting a range of encode, decode,
and transcode operations for most major video codec standards. The main video Codec standards
supported in hardware are MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP, RV9/10, AVS-1.0,
and ON2 VP6.2/VP7.
The HDVICP2 hardware accelerator is composed of the following elements:
•
Motion estimation acceleration engine
•
Loop filter acceleration engine
•
Sequencer, including its memories and an interrupt controller
•
Intra-prediction estimation engine
•
Calculation engine
•
Motion compensation engine
•
Entropy coder/decoder
•
Video Direct Memory Access (DMA)
•
Synchronization boxes
•
Shared L2 controller
•
Local interconnect
For more details on the HDVICP2, see the HD Video Coprocessor SubSystem section of the Chip Level
Resources chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual
(Literature Number: SPRUGZ8).
Copyright © 2011–2013, Texas Instruments Incorporated
Device Overview
21
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Product Folder Links: TMS320DM8148 TMS320DM8147



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