L9659 datasheet(30/51 Pages) STMICROELECTRONICS

30 / 51 page

Functional description

L9659

30/51

Doc ID 022048 Rev 2

On the next falling edge of CS_D, comparator latched data are captured and reported to

MISO response. The results will remain latch until the next test is initiated (diagnostic write

command). If the test is in progress then a bit is used in the response to indicate the test

completion. If the FET under test is working properly then the results will indicate a “Short to

Ground” for LS test and “Short to Battery” for HS test. If a leakage is present prior to the test

or FENx is asserted then both “Short to Ground” and Short to Battery” will be indicated in

the response for either a LS or HS FET test.

For all conditions the current on SQHx/SQLx will never exceed ISVRCM. On the squib lines

there will be highertransient currents due to the presence of the filter capacitor.

High side safing diagnostics

When the command is received the L9659 will activate IHSS on the selected VRESx. The

diagnostics will measure the difference between VSDIAG and VRESx. The internal

comparator will detect open, short or normal condition based on the differential voltage

between VSDIAG and VRESx.

The results will be reported in the next SPI message using bits HSS1 and HSS0 as

indicated in the following table. Once the command is issued the voltages will be captured

on the next falling edge of CS_D.

Voltage measurement diagnostics (VRESx)

When the command is received the L9659 will activate a comparator for the selected

channel. A 2 bit indication of the state of the VRESx pins will be reported as indicated below.

The results will be reported in the next SPI message. Once the command is issued the

voltages will be captured on the next falling edge of CS_D.

Loss of power ground

When any of the power grounds (GND0 – 7) are lost, no deployment can occur on the

respective deployment channels because the low side driver will be inactive. The high side

driver for the respective channel can still be activated.

A loss of ground condition on one or several channels will not affect the operation of the

remaining channels. When a loss of ground condition occurs, the source of the low side

MOS will be floating. In this case, no current will flow through the low side driver.

Table 12.

Diagnostic Mode HSS selection

Condition

HSS1

HSS0

(VSDIAG-VRESx) < VHSSSHORT_th

VHSSSHORT_th < (VSDIAG-VRESx) < VHSSOPEN_th

VHSSOPEN_th < (VSDIAG-VRESx)

Table 13.

Diagnostic mode 3 VRESx selection

Condition

VR1

VR0

VRESx < VVRESXLO_th

VVRESXLO_th < VRESx < VVRESXHI_th

VVRESXHI_th < VRESx

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