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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TAS5721 bảng dữ liệu(PDF) 9 Page - Texas Instruments |
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TAS5721 bảng dữ liệu(HTML) 9 Page - Texas Instruments |
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9 / 78 page  9 TAS5721 www.ti.com SLOS739A – JULY 2012 – REVISED MARCH 2016 Product Folder Links: TAS5721 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated 7.8 Headphone Amplifier and Line Driver Characteristics TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PoHP Power output per channel of headphone amplifier DRVDD = 3.3 V (RHP = 32; THD = 1%) 50 mW AVDR Gain for headphone amplifier and line driver Adjustable through Rin and Rfb - dB SNRHP Signal-to-noise ratio (headphone mode) Rhp = 32 101 dB SNRLD Signal-to-noise ratio (line driver mode) 2-VRMS output 105 dB 7.9 Protection Characteristics TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified). MIN TYP MAX UNIT Vuvp(fall) Undervoltage protection limit PVDD falling 4 V Vuvp(rise) Undervoltage protection limit PVDD rising 4.1 V OTE Overtemperature error threshold 150 °C ΔOTE Variation in overtemperature detection circuit ±15 °C IOCE Overcurrent limit protection threshold 3 A tOCE Overcurrent response time 150 ns 7.10 I 2C Serial Control Port Requirements and Specifications PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified). MIN MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tw(H) Pulse duration, SCL high 0.6 μs tw(L) Pulse duration, SCL low 1.3 μs tr Rise time, SCL and SDA 300 ns tf Fall time, SCL and SDA 300 ns tsu1 Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 0 ns t(buf) Bus free time between stop and start conditions 1.3 μs tsu2 Setup time, SCL to start condition 0.6 μs th2 Hold time, start condition to SCL 0.6 μs tsu3 Setup time, SCL to stop condition 0.6 μs CL Load capacitance for each bus line 400 pF 7.11 Serial Audio Port Timing PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48 kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with recommended operating conditions (unless otherwise specified). MIN TYP MAX UNIT fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS CL = 30 pF 1.024 12.288 MHz tsu1 Setup time, LRCLK to SCLK rising edge 10 ns th1 Hold time, LRCLK from SCLK rising edge 10 ns tsu2 Setup time, SDIN to SCLK rising edge 10 ns th2 Hold time, SDIN from SCLK rising edge 10 ns |
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