TAS5721 datasheet(48/78 Pages) TI1

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TAS5721

SLOS739A – JULY 2012 – REVISED MARCH 2016

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(1)

Default values are in bold.

9.6.10 Modulation Limit Register (0x10)

The modulation limit is the maximum duty cycle of the PWM output waveform. It is important to note that for any

applications with PVDD greater than 18 V, the maximum modulation index must be set to 93.8%.

Table 14. Modulation Limit Register (0x10)

MODULATION LIMIT

–

99.2%

–

98.4%

–

97.7% (1)

–

96.9%

–

96.1%

–

95.3%

–

94.5%

–

93.8%

–

RESERVED

(1)

Default values are in bold.

9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

Table 15. Channel Interchannel Delay Register Format

SUBADDRESS

Delay = (value) × 4 DCLKs

0x11

–

Default value for channel 1 (1)

0x12

–

Default value for channel 2 (1)

0x13

–

Default value for channel 1 (1)

0x14

–

Default value for channel 2 (1)

RANGE OF VALUES FOR 0x11 - 0x14

–

Minimum absolute delay, 0 DCLK cycles

–

Maximum positive delay, 31 × 4 DCLK cycles

–

Maximum negative delay, –32 × 4 DCLK cycles

RESERVED

The ICD settings have high impact on audio performance (for example, dynamic range, THD+N, crosstalk, and

so forth). Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for AD

mode. If used in BD mode, then update these registers before coming out of all-channel shutdown.

AD MODE

BD MODE

0x11

0x12

0x13

0x14

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