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TAS5721 bảng dữ liệu(PDF) 39 Page - Texas Instruments

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tên linh kiện TAS5721
Giải thích chi tiết về linh kiện  Digital Audio Power Amplifier With EQ, DRC, 2.1 Support, and Headphone/Line Driver
PDF  78 Pages
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Trang chủ  http://www.ti.com
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TAS5721 bảng dữ liệu(HTML) 39 Page - Texas Instruments

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TAS5721
www.ti.com
SLOS739A – JULY 2012 – REVISED MARCH 2016
Product Folder Links: TAS5721
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
Register Maps (continued)
Table 4. Serial Control Interface Register Summary (continued)
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
CONTENTS
DEFAULT
VALUE
(1)
Reserved registers should not be accessed.
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Channel 3 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0B–0x0D
1
Reserved(1)
0x0E
Volume configuration
register
1
Description shown in subsequent section
0x91
0x0F
1
Reserved(1)
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
0x15–0x18
1
Reserved(1)
0x19
PWM channel shutdown
group register
1
Description shown in subsequent section
0x30
0x1A
Start/stop period register
1
Description shown in subsequent section
0x0F
0x1B
Oscillator trim register
1
Description shown in subsequent section
0x82
0x1C
BKND_ERR register
1
Description shown in subsequent section
0x02
0x1D–0x1F
1
Reserved(1)
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Ch 4 source select register
4
Description shown in subsequent section
0x0000 4303
0x22–0x24
4
Reserved(1)
0x25
PWM MUX register
4
Description shown in subsequent section
0x0102 1345
0x26–0x28
4
Reserved(1)
0x29
ch1_bq[0]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x2A
ch1_bq[1]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x2B
ch1_bq[2]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x2C
ch1_bq[3]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000



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