TAS5721 datasheet(8/78 Pages) TI1

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TAS5721

SLOS739A – JULY 2012 – REVISED MARCH 2016

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(1)

For clocks related to the serial audio port, please see Serial Audio Port Timing

7.6 Master Clock Characteristics

(1)

PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, external components per Typical Application diagrams, and in accordance

with recommended operating conditions (unless otherwise specified).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fMCLK

MCLK frequency

2.8224

24.576

MHz

MCLK duty cycle

40%

50%

60%

tr(MCLK) / tf(MCLK)

Rise/fall time for MCLK

(1)

Power levels are thermally limited.

(2)

SNR is calculated relative to 0-dBFS input level.

7.7 Speaker Amplifier Characteristics

TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal =1 kHz sine wave, BTL, AD mode, fS = 48

kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per Typical Application diagrams, and in accordance with

recommended operating conditions (unless otherwise specified).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PoSPK

(BTL)

Power output per channel of

speaker amplifier when used in

BTL mode (1)

PVDD = 18 V, RSPK = 8Ω, 1-kHz input signal

PVDD = 12 V, RSPK = 8Ω, 10% THD+N, 1-kHz

input signal

8.8

PVDD = 12 V, RSPK = 8Ω, 7% THD+N, 1-kHz input

signal

8.3

PVDD = 8 V, RSPK = 8Ω, 10% THD+N, 1-kHz input

signal

PVDD = 8 V, RSPK = 8Ω, 7% THD+N, 1-kHz input

signal

3.8

PoSPK

(PBTL)

Power output per channel of

speaker amplifier when used in

PBTL mode (1)

PVDD = 12 V, RSPK = 4Ω,

10% THD+N, 1-kHz input signal

PVDD = 12 V, RSPK = 4Ω,

7% THD+N, 1-kHz input signal

PVDD = 18 V, RSPK = 4Ω,

1-kHz input signal

PoSPK

(SE)

Power output per channel of

speaker amplifier when used in

SE mode (1)

PVDD = 12 V, RSPK = 4 Ω,

10% THD+N, 1-kHz input signal

4.3

PVDD = 24 V, RSPK = 4 Ω,

10% THD+N, 1-kHz input signal

5.5

THD+N

Total harmonic distortion +

noise

PVDD = 18 V, PO = 1 W

0.07%

PVDD = 12 V, PO = 1 W

0.11%

PVDD = 8 V, PO = 1 W

0.2%

ICN

Idle channel noise

A-weighted

μV

Crosstalk

PO = 1 W, f = 1 kHz (BD Mode), PVDD = 24 V

PO =1 W, f = 1 kHz (AD Mode), PVDD = 24 V

SNR

Signal-to-noise ratio(2)

A-weighted, f = 1 kHz, maximum power at THD <

106

fPWM

Output switching frequency

11.025/22.05/44.1-kHz data rate ±2%

352.8

kHz

48/24/12/8/16/32-kHz data rate ±2%

384

IPVDD

Supply current

No load (PVDD)

Normal mode

Reset (RST = low, PDN =

high)

rDS(on)

Drain-to-source resistance (for

each of the Low-Side and High-

Side Devices)

TJ = 25°C, includes metallization resistance

200

RPD

Internal pulldown resistor at the

output of each half-bridge

Connected when drivers are in the high-impedance

state to provide bootstrap capacitor charge.

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