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EM351-RTR bảng dữ liệu(PDF) 149 Page - Silicon Laboratories

tên linh kiện EM351-RTR
Giải thích chi tiết về linh kiện  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  241 Pages
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nhà sản xuất  SILABS [Silicon Laboratories]
Trang chủ  http://www.silabs.com
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EM351-RTR bảng dữ liệu(HTML) 149 Page - Silicon Laboratories

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149
Rev 1.3
TIM_ETF
[11:8]
RW
External Trigger Filter.
This defines the frequency used to sample the ETRP signal, Fsampling, and
the length of the digital filter applied to ETRP. The digital filter is made of an
event counter in which N events are needed to validate a transition on the
output:
0000: Fsampling = PCLK, no filtering.
0001: Fsampling = PCLK, N = 2.
0010: Fsampling = PCLK, N = 4.
0011: Fsampling = PCLK, N = 8.
0100: Fsampling = PCLK/2, N = 6.
0101: Fsampling = PCLK/2, N = 8.
0110: Fsampling = PCLK/4, N = 6.
0111: Fsampling = PCLK/4, N = 8.
1000: Fsampling = PCLK/8, N = 6.
1001: Fsampling = PCLK/8, N = 8.
1010: Fsampling = PCLK/16, N = 5.
1011: Fsampling = PCLK/16, N = 6.
1100: Fsampling = PCLK/16, N = 8.
1101: Fsampling = PCLK/32, N = 5.
1110: Fsampling = PCLK/32, N = 6.
1111: Fsampling = PCLK/32, N = 8.
Note:
PCLK is 12 MHz when the EM35x is using the 24 MHz crystal oscillator, and
6 MHz if using the 12 MHz RC oscillator.
TIM_MSM
[7]
RW
Master/Slave Mode.
0: No action.
1: The effect of an event on the trigger input (TRGI) is delayed to allow exact
synchronization between the current timer and the slave (through TRGO). It is
useful for synchronizing timers on a single external event.
TIM_TS
[6:4]
RW
Trigger Selection.
This bit field selects the trigger input used to synchronize the counter.
000 : Internal Trigger 0 (ITR0).
100 : TI1 Edge Detector (TI1F_ED).
101 : Filtered Timer Input 1 (TI1FP1).
110 : Filtered Timer Input 2 (TI2FP2).
111 : External Trigger input (ETRF).
Note:
These bits must be changed only when they are not used (when
TIM_SMS = 000) to avoid detecting spurious edges during the transition.
Bitname
Bitfield
Access
Description



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