SC2200 datasheet(96/433 Pages) NSC

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Revision 3.0

General Configuration Block (Continued)

3.5.4

SuperI/O Clocks

The SuperI/O module requires a 48 MHz input for Fast

infrared (FIR), UART, and other functions. This clock is sup-

plied by PLL4 using a multiplier value of 576/(108x3) to

generate 48 MHz.

3.5.5

Core Logic Module Clocks

The Core Logic module requires the following clock

sources:

Real-Time Clock (RTC)

RTC requires a 32.768 KHz clock which is supplied directly

from an internal low-power crystal oscillator. This oscillator

uses battery power and has very low current consumption.

USB

The USB requires a 48 MHz input which is supplied by

PLL4. The required total frequency accuracy and slow jitter

for USB is 500 PPM; edge to edge jitter is

±1.2%.

ACPI

The ACPI logic block uses a 14.32 MHz clock supplied by

PLL6. PLL6 creates this clock from the 32.768 KHz clock,

with a multiplier value of 6992/4 to output a 57.278 MHz

clock that is divided by 4.

External PCI

The PCI Interface uses a 33.3 MHz clock that is created by

PLL5 and divided by 2. PLL5 uses the 27 MHz clock, to

output a 66.67 MHz clock. PLL5 has a frequency accuracy

± 0.1%.

AC97

The SC2200 generates the 24.576 MHz clock required by

the audio codec. Therefore, no crystal need be included for

the audio codec on the system board.

PLL3 uses the crystal oscillator clock, to generate a 24.576

MHz clock. This clock is driven on the AC97_CLK ball. The

accuracy of the clock supplied by the SC2200 is 50 PPM.

3.5.6

Video Processor Clocks

The Video processor requires the following clock sources:

Dot

The Dot clock is generated by PLL2. It is supplied to the

Display Controller in the GX1 module (DCLK) that creates

the pixel information, and is returned to the Graphics block

(PCLK) with this information. PLL2 uses the 27 MHz clock

to generate the Dot clock.

Video

The Video clock source depends on the source of the video

data.

• If the video data is coming from the GX1 module

(Capture Video mode), the video clock is generated by

the Display Controller.

• If the video data is coming directly from the VIP block

(Direct Video mode), the Video Clock is generated by

the VIP block.

3.5.7

Clock Registers

Table 3-8 describes the registers of the clock generator and

PLL.

Table 3-8. Clock Generator Configuration

Bit

Description

Offset 10h

Maximum Core Clock Multiplier Register - MCCM (RO)

Reset Value: Strapped Value

This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI clock

multiplied by this value.

7:4

Reserved.

3:0

MCM (Maximum Clock Multiplier). This 4-bit value is the maximum multiplier value allowed for the core clock generator. It

is derived from strap pins CLKSEL[3:0] based on the multiplier value in Table 3-7 on page 95.

Offset 11h

Reserved - RSVD

Offset 12h

PLL Power Control Register - PPCR (R/W)

Reset Value: 2Fh

This register controls operation of the PLLs.

Reserved.

EXPCID (Disable External PCI Clock).

0: External PCI clock is enabled.

1: External PCI clock is disabled.

GPD (Disable Graphic Pixel Reference Clock).

0: PLL2 input clock is enabled.

1: PLL2 input clock is disabled.

Reserved.

PLL3SD (Shut Down PLL3). AC97 codec clock.

0: PLL3 is enabled.

1: PLL3 is shutdown.

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