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SC2200 bảng dữ liệu(PDF) 52 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện SC2200
Giải thích chi tiết về linh kiện  Thin Client On a Chip
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52
Revision 3.0
Signal Definitions (Continued)
2.3
MULTIPLEXING CONFIGURATION
The tables that follow list multiplexing options and their
configurations. Certain multiplexing options may be chosen
per signal; others are available only for a group of signals.
Where ever a GPIO pin is multiplexed with another func-
tion, there is an optional pull-up resistor on this pin; after
system reset, the pull-up is present. This pull-up resistor
can be disabled by writing Core Logic registers. The con-
figuration is without regard to the selected ball function.
The above applies to all pins multiplexed with GPIO,
except GPIO12, GPIO13, and GPIO16.
Table 2-7. Two-Signal/Group Multiplexing
EBGA
TEPBGA
Default
Alternate
Signal
Configuration
Signal
Configuration
Ball No.
IDE
TFT, CRT, PCI, GPIO, System
A26
AD3
IDE_ADDR0
PMR[24] = 0
TFTD3
PMR[24] = 1
C26
AE1
IDE_ADDR1
TFTD2
C17
U2
IDE_ADDR2
TFTD4
B24
AC3
IDE_DATA0
TFTD6
A24
AC1
IDE_DATA1
TFTD16
D23
AC2
IDE_DATA2
TFTD14
C23
AB4
IDE_DATA3
TFTD12
B23
AB1
IDE_DATA4
FP_VDD_ON
A23
AA4
IDE_DATA5
CLK27M
C22
AA3
IDE_DATA6
IRQ9
B22
AA2
IDE_DATA7
INTD#
A21
Y3
IDE_DATA8
GPIO40
C20
Y2
IDE_DATA9
DDC_SDA
A20
Y1
IDE_DATA10
DDC_SCL
C19
W4
IDE_DATA11
GPIO41
B19
W3
IDE_DATA12
TFTD13
A19
V3
IDE_DATA13
TFTD15
C18
V2
IDE_DATA14
TFTD17
B18
V1
IDE_DATA15
TFTD7
C21
Y4
IDE_IOR0#
TFTD10
A25
AD1
IDE_IORDY0
TFTD11
C24
AC4
IDE_DREQ0
TFTD8
D24
AD2
IDE_IOW0#
TFTD9
A27
AF2
IDE_CS0#
TFTD5
C16
P2
IDE_CS1#
TFTDE
C25
AD4
IDE_DACK0#
TFTD0
A22
AA1
IDE_RST#
TFTDCK
D25
AF1
IRQ14
TFTD1
Ball No.
Sub-ISA
GPIO
H1
D11
TRDE#
PMR[12] = 0
GPIO0
PMR[12] = 1



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