IOBUS0 datasheet(29/88 Pages) FTDI

29 / 88 page

C opyright © Future T ec hnology Devic es I nternational Limited

Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

V ers ion 1 .7

Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43

5.1 I/O Peripherals Signal Names

Peripheral

Signal Name

Outputs

Inputs

Description

Debugger

debug_if

debugger interface

UART

uart_txd

Transmit asynchronous data output

uart_rts#

Request to send control output

uart_dtr#

Data acknowledge (data terminal ready control) output

uart_tx_active

Enable transmit data for RS485 designs

uart_rxd

Receive asynchronous data input

uart_cts#

Clear to send control input

uart_dsr#

Data request (data set ready control) input

uart_ri#

Ring indicator control input

uart_dcd#

Data carrier detect control input

FIFO

fifo_data

FIFO data bus

fifo_txe#

When high, do not write data into the FIFO. When low,

data can be written into the FIFO by strobing WR high,

then low.

fifo_rxf#

When high, do not read data from the FIFO. When low,

there is data available in the FIFO which can be read by

strobing RD# low, then high.

fifo_wr#

Writes the data byte on the D0...D7 pins into the

transmit FIFO buffer when WR goes from high to low.

fifo_rd#

Enables the current FIFO data byte on D0...D7 when low.

Fetches the next FIFO data byte (if available) from the

receive FIFO buffer when RD# goes from high to low

fifo_oe#

FIFO output enable – synchronous FIFO only

fifo_clkout

FIFO clock out – synchronous FIFO only

GPIO

gpio

General purpose I/O

SPI Slave 0

spi_s0_clk

SPI clock input – slave 0

spi_s0_ss#

SPI chip select input – slave 0

spi_s0_mosi

SPI master out serial in – slave 0

spi_s0_miso

SPI master in slave out – slave 0

SPI Slave 1

spi_s1_clk

SPI clock input – slave 1

spi_s1_ss#

SPI chip select input – slave 1

spi_s1_mosi

Master out slave in – slave 1

spi_s1_miso

Master in slave out – slave 1

SPI Master

spi_m_clk

SPI clock input – master

spi_m_mosi

Master out slave in - master

spi_m_miso

Master in slave out - master

spi_m_ss_0#

Active low slave select 0 from master to slave 0

spi_m_ss_1#

Active low slave select 1 from master to slave 1

PWM

pwm

Pulse width modulation

Table 5.1 I/O Peripherals Signal Names

Note: # is used to indicate an active low signal.

IOBUS0 bảng dữ liệu(PDF) 29 Page - Future Technology Devices International Ltd.

IOBUS0 bảng dữ liệu(HTML) 29 Page - Future Technology Devices International Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

bảng dữ liệu tải về

Link URL