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WM9713 bảng dữ liệu(PDF) 94 Page - Wolfson Microelectronics plc |
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WM9713 bảng dữ liệu(HTML) 94 Page - Wolfson Microelectronics plc |
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94 / 111 page  WM9713L Preliminary Technical Data 1 PTD, March 2004, Rev 2.2 94 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 15:14 ID 00 Indicates that the WM9713L is configured as the primary codec in the system. 11:10 REV 01 Indicates that the WM9713L conforms to AC’97 Rev2.2 9 AMAP 0 Indicates that the WM9713L does not support slot mapping 8 LDAC 0 Indicates that the WM9713L does not have an LFE DAC 7 SDAC 0 Indicates that the WM9713L does not have Surround DACs 6 CDAC 0 Indicates that the WM9713L does not have a Centre DAC 3 VRM 0 Indicates that the WM9713L does not have a dedicated, variable rate microphone ADC 2 SPDIF 1 Indicates that the WM9713L supports SPDIF output 1 DRA 0 Indicates that the WM9713L does not support double rate audio 28h 0 VRA 1 Indicates that the WM9713L supports variable rate audio Intel’s AC’97 Component Specification, Revision 2.2, page 59 Register 28h is a read-only register that indicates to the driver which advanced AC’97 features the WM9713L supports. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 10 SPCV 1 (valid) SPDIF validity bit (read-only) 5:4 SPSA 01 (slots 6, 9) Controls SPDIF slot assignment. 00=slots 3 and 4, 01=6/9, 10=7/8, 11=10/11 2 SEN 0 (OFF) Enables SPDIF output enable 2Ah 0 VRA 0 (OFF) Enables variable rate audio Digital Audio (SPDIF) Output Register 2Ah controls the SPDIF output and variable rate audio. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 2Ch all DACSR BB80h Controls stereo DAC sample rate 2Eh all AUXDACSR BB80h Controls auxiliary DAC sample rate 32h all ADCSR BB80h Controls audio ADC sample rate Variable Rate Audio / Sample Rate Conversion Note: The VRA bit in register 2Ah must be set first to obtain sample rates other than 48kHz Registers 2Ch, 2Eh 32h and control the sample rates for the stereo DAC, auxiliary DAC and audio ADC, respectively. |
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