MB95F613K datasheet(32/110 Pages) CYPRESS

32 / 110 page

Document Number: 002-04698 Rev. *A

Page 32 of 110

PRELIMINARY

MB95610H Series

(Continued)

■ R/W access symbols

■ Initial value symbols

Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.

Address

abbreviation

R/W

Initial value

0x0FB7

LCDCE6

LCDC enable register 6

R/W

0b00000000

0x0FB8

LCDCE7

LCDC enable register 7

R/W

0b00000000

0x0FB9

LCDCE8

LCDC enable register 8

R/W

0b00000000

0x0FBA

LCDCE9

LCDC enable register 9

R/W

0b00000000

0x0FBB

LCDCB1

LCDC blinking setting register 1

R/W

0b00000000

0x0FBC

LCDCB2

LCDC blinking setting register 2

R/W

0b00000000

0x0FBD

0x0FE0

LCDRAM

LCDC display RAM

4 COM mode: 0x0FBD to 0x0FD6 (26 bytes)

8 COM mode: 0x0FC1 to 0x0FE0 (32 bytes)

R/W

0b00000000

0x0FE1

—

(Disabled)

—

0x0FE2

EVCR

Event counter control register

R/W

0bXXXXXXX0

0x0FE3

WCDR

Watch counter data register

R/W

0b00111111

0x0FE4

CRTH

Main CR clock trimming register (upper)

R/W

0b000XXXXX

0x0FE5

CRTL

Main CR clock trimming register (lower)

R/W

0b000XXXXX

0x0FE6

—

(Disabled)

—

0x0FE7

CRTDA

Main CR clock temperature dependent adjustment register

R/W

0b000XXXXX

0x0FE8

SYSC

System configuration register

R/W

0b11000011

0x0FE9

CMCR

Clock monitoring control register

R/W

0b00000000

0x0FEA

CMDR

Clock monitoring data register

0b00000000

0x0FEB

WDTH

Watchdog timer selection ID register (upper)

0bXXXXXXXX

0x0FEC

WDTL

Watchdog timer selection ID register (lower)

0bXXXXXXXX

0x0FED,

0x0FEE

—

(Disabled)

—

0x0FEF

WICR

Interrupt pin selection circuit control register

R/W

0b01000000

0x0FF0

0x0FFF

LCDRAM

LCDC display RAM

4 COM mode: Unused

8 COM mode: 0x0FF0 to 0x0FFF (16 bytes)

R/W

0b00000000

R/W

: Readable/Writable

: Read only

: The initial value of this bit is “0”.

: The initial value of this bit is “1”.

: The initial value of this bit is undefined.

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