SST38VF6401 datasheet(9/64 Pages) MICROCHIP

9 / 64 page

DS-20005015B

08/15

64 Mbit (x16) Advanced Multi-Purpose Flash Plus

SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404

Not Recommended for New Designs

Device Operation

The memory operations functions of these devices are initiated using commands written to the device

using standard microprocessor Write sequences. A command is written by asserting WE# low while

keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs

last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST38VF6401/6402/6403/6404 also have the Auto Low Power mode which puts the device in a

near-standby mode after data has been accessed with a valid Read operation. This reduces the IDD

active read current from typically 4 mA to typically 3 µA. The Auto Low Power mode reduces the typical

IDD active read current to the range of 2 mA/MHz of Read cycle time. The device requires no access

time to exit the Auto Low Power mode after any address transition or control signal transition used to

initiate another Read cycle. The device does not enter Auto-Low Power mode after power-up with CE#

held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST38VF6401/6402/6403/6404 is controlled by CE# and OE#, both of which

have to be low for the system to obtain data from the outputs. CE# is used for device selection. When

CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and

is used to gate data from the output pins. The data bus is in high impedance state when either CE# or

OE# is high. Refer to Figure 5, the Read cycle timing diagram, for further details.

Page Read

The Page Read operation utilizes an asynchronous method that enables the system to read data from

the SST38VF6401/6402/6403/6404 at a faster rate. This operation allows users to read a four-word

page of data at an average speed of 41.25 ns per word.

In Page Read, the initial word read from the page requires TACC to be valid, while the remaining three

words in the page require only TPACC. All four words in the page have the same address bits, A21-A2,

which are used to select the page. Address bits A1 and A0 are toggled, in any order, to read the words

within the page.

The Page Read operation of the SST38VF6401/6402/6403/6404 is controlled by CE# and OE#. Both

CE# and OE# must be low for the system to obtain data from the output pins. CE# controls device

selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the

output control and is used to gate data from the output pins. The data bus is in high impedance state

when either CE# or OE# is high. Refer to Figure 6, the Page Read cycle timing diagram, for further

details.

Word-Program Operation

The SST38VF6401/6402/6403/6404 can be programmed on a word-by-word basis. Before program-

ming, the sector where the word exists must be fully erased. The Program operation is accomplished

in three steps. The first step is the three-byte load sequence for Software Data Protection. The second

step is to load word address and word data. During the Word-Program operation, the addresses are

latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the ris-

ing edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation

which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program

operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for WE# and CE# con-

trolled Program operation timing diagrams and Figure 24 for flowcharts.

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