LAN9211 datasheet(131/147 Pages) SMSC

131 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

SMSC LAN9211

131

Revision 2.9 (03-01-12)

DATASHEET

6.4

RX Data FIFO Direct PIO Reads

In this mode the upper address inputs are not decoded, and any read of the LAN9211 will read the

RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is

normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is

useful when the host processor must increment its address when accessing the LAN9211. Timing is

identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address

lines.

Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.

Note: The “Data Bus” width is 16 bits.

Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The

cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-

asserted in any order.

Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing

Table 6.5 RX Data FIFO Direct PIO Read Timing

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tcycle

Read Cycle Time

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address, FIFO_SEL Setup to nCS, nRD Valid

tah

Address, FIFO_SEL Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Data Bus

nCS, nRD

FIFO_SEL

A[2:1]

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