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LAN9211 bảng dữ liệu(PDF) 134 Page - SMSC Corporation

tên linh kiện LAN9211
Giải thích chi tiết về linh kiện  High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
PDF  147 Pages
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nhà sản xuất  SMSC [SMSC Corporation]
Trang chủ  http://www.smsc.com
Logo SMSC - SMSC Corporation

LAN9211 bảng dữ liệu(HTML) 134 Page - SMSC Corporation

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
Revision 2.9 (03-01-12)
134
SMSC LAN9211
DATASHEET
6.7
TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9211 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9211. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note: The “Data Bus” width is 16 bits.
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order.
Figure 6.6 TX Data FIFO Direct PIO Write Timing
Table 6.8 TX Data FIFO Direct PIO Write Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcycle
Write Cycle Time
45
ns
tcsl
nCS, nWR Assertion Time
32
ns
tcsh
nCS, nWR Deassertion Time
13
ns
tasu
Address, FIFO_SEL Setup to nCS, nWR Assertion
0
ns
tah
Address, FIFO_SEL Hold Time
0
ns
tdsu
Data Setup to nCS, nWR Deassertion
7
ns
tdh
Data Hold Time
0
ns
Data Bus
nCS, nWR
FIFO_SEL
A[2:1]



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