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LAN9211 bảng dữ liệu(PDF) 129 Page - SMSC Corporation

tên linh kiện LAN9211
Giải thích chi tiết về linh kiện  High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
PDF  147 Pages
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nhà sản xuất  SMSC [SMSC Corporation]
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LAN9211 bảng dữ liệu(HTML) 129 Page - SMSC Corporation

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High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9211
129
Revision 2.9 (03-01-12)
DATASHEET
6.2
PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters
in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing
diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both
of these control signals must go high between cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read
cycles.
Note: The “Data Bus” width is 16 bits
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either
or both nCS and nRD are deasserted. They may be asserted and deasserted in any order.
Figure 6.1 PIO Read Cycle Timing
Table 6.3 PIO Read Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcycle
Read Cycle Time
45
ns
tcsl
nCS, nRD Assertion Time
32
ns
tcsh
nCS, nRD Deassertion Time
13
ns
tcsdv
nCS, nRD Valid to Data Valid
30
ns
tasu
Address Setup to nCS, nRD Valid
0
ns
tah
Address Hold Time
0
ns
tdon
Data Buffer Turn On Time
0
ns
tdoff
Data Buffer Turn Off Time
7
ns
tdoh
Data Output Hold Time
0
ns
Data Bus
nCS, nRD
A[7:1]



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