LAN8742AI-CZ datasheet(110/124 Pages) MICROCHIP

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LAN8742A/LAN8742Ai

DS00001989A-page 110

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5.6.4

RMII INTERFACE TIMING

5.6.4.1

RMII Timing (REF_CLK Out Mode)

The 50 MHz REF_CLK OUT timing applies to the case when nINTSEL is pulled-low. In this mode, a 25 MHz crystal or

clock oscillator must be input on the XTAL1/CLKIN and XTAL2 pins. For more information on REF_CLK Out Mode, see

Section 3.7.4.2, "REF_CLK Out Mode".

Note 1: Timing was designed for system load between 10 pf and 25 pf.

Note:

The CRS_DV pin performs both carrier sense and data valid functions. CRS_DV is asserted asynchro-

nously on detection of carrier due to the criteria relevant to the operating mode. If the PHY has additional

bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device will assert

CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and deassert CRS_DV on

cycles of REF_CLK which present the first di-bit of a nibble. For additional information, refer to the RMII

specification.

FIGURE 5-4:

RMII TIMING (REF_CLK OUT MODE)

TABLE 5-12:

RMII TIMING VALUES (REF_CLK OUT MODE)

Symbol

Description

Min.

Max.

Unit

Note

tclkp

REFCLKO period

tclkh

REFCLKO high time

tclkp*0.4

tclkp*0.6

tclkl

REFCLKO low time

tclkp*0.4

tclkp*0.6

toval

RXD[1:0], RXER, CRS_DV output valid from ris-

ing edge of REFCLKO

7.0

(see Note 1)

toinvld

RXD[1:0], RXER, CRS_DV output invalid from

rising edge of REFCLKO

3.0

(see Note 1)

tsu

TXD[1:0], TXEN setup time to rising edge of

REFCLKO

7.5

(see Note 1)

tihold

TXD[1:0], TXEN input hold time after rising edge

of REFCLKO

2.0

(see Note 1)

tclkh

tclkl

tclkp

toval

toinvld

toval

toinvld

tsu tihold

tihold

tsu

tihold

REFCLKO

(OUTPUT)

RXD[1:0], RXER

(OUTPUTS)

CRS_DV

(OUTPUT)

TXD[1:0]

(INPUTS)

TXEN

(INPUT)

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