LAN8742AI-CZ datasheet(108/124 Pages) MICROCHIP

108 / 124 page

LAN8742A/LAN8742Ai

DS00001989A-page 108

 2013-2015 Microchip Technology Inc.

5.6

AC Specifications

This section details the various AC timing specifications of the device.

5.6.1

EQUIVALENT TEST LOAD

Output timing specifications assume a 25 pF equivalent test load, unless otherwise noted, as illustrated in Figure 5-1

below.

5.6.2

POWER SEQUENCE TIMING

This diagram illustrates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and magnetics power

supplies can turn on in any order provided they all reach operational levels within the specified time period tpon. Device

power supplies can turn off in any order provided they all reach 0 volts within the specified time period tpoff.

It is acceptable for the VDD1A/VDD2A supply to remain powered up while the VDDCR and VDDIO supplies are at zero

volts for a period not to exceed 750 ms. In this case, nRESET must be asserted while VDDCR and/or VDDIO is off, and

must remain asserted for a minimum of 50 ms after the VDDCR and VDDIO supplies reach operational level. Addition-

ally, VDDIO must come up with or after the VDDCR supply. Configuration straps must meet the requirements specified

in Section 5.6.3, "Power-On nRST & Configuration Strap Timing".

FIGURE 5-1:

OUTPUT EQUIVALENT TEST LOAD

FIGURE 5-2:

POWER SEQUENCE TIMING

TABLE 5-10:

POWER SEQUENCE TIMING VALUES

Symbol

Description

Min.

Typ.

Max.

Unit

tpon

Power supply turn on time

tpoff

Power supply turn off time

500

Note:

When the internal regulator is disabled, a power-up sequencing relationship exists between VDDCR and

the 3.3 V power supply. For additional information refer to Section 3.7.3, "REGOFF: Internal +1.2 V Regu-

lator Configuration".

25 pF

OUTPUT

VDDIO

Magnetics

Power

tpon

tpoff

VDD1A,

VDD2A

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