DDP3310B datasheet(5/60 Pages) MICRONAS

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ADVANCE INFORMATION

DDP 3310B

Micronas

1.2. System Architecture

The DDP 3310B is a mixed-signal IC containing the

entire digital video component processing such as

chroma transient improvement (CTI), adaptive luma

peaking, and a non-linear ‘Panorama’ aspect ratio con-

version. All deflection related signals can be adapted

to different scan rates. The analog section contains all

analog interface components and an ADC, to compen-

sate long term changes of the picture tube parameters

and extreme high-tension effects. Fig. 1–1 shows the

block diagram of the single-chip Display and Deflection

Processor.

1.3. System Application

Fig. 1–2 depicts several DDP applications. Since the

DDP functions as a video back-end, it must be comple-

mented with additional functionality to form a complete

TV set.

The VPC 32xx family processes all worldwide analog

video signals (including the European PALplus) and

allows non-linear Panorama aspect ratio conversion.

Thus, 4:3 and 16:9 systems can easily be configured

by software. The aspect ratio scaling is also used as a

sample rate converter to provide a line-locked digital

component output bus (YCrCb) compliant to ITU-R-601.

All video processing and line-locked clock/data gener-

ation is derived from a single 20.25-MHz crystal. An

optional adaptive 2H/4H comb filter (VPC 32xx) per-

forms Y/C separation for PAL and NTSC and all of their

substandards.

The VPC 32xxD and the CIP 3250A provide a high-

quality analog RGB interface with character insertion

capability. This allows appropriate processing of exter-

nal sources such as MPEG 2 set-top boxes in trans-

parent (4:2:2) quality. Furthermore, it translates RGB/

Fast-Blank signals to the common digital video bus

and makes those signals available for 100-Hz process-

ing. In some European countries (Italy), this feature is

mandatory.

The IP indicates memory-based image processing,

such as scan rate conversion, vertical processing

(Zoom), or PAL+ reconstruction.

Examples:

– Europe: 15 kHz/ 50 Hz

→ 32 kHz/100 Hz interlaced

– US: 15 kHz/60 Hz

→ 31 kHz/120 Hz non-interlaced

Note: The DDP 3310B and the VPC 32xx families

support memory-based applications through line-

locked clocks, syncs, and data. The CIP 3250A may

run either with the native DIGIT3000 clock but also

with a line-locked clock system.

Fig. 1–2: DDP 3310B applications

VPC

32xx

PAL+

100 Hz

✔

CVBS

RGB

DDP

3310B

CIP

3250A

RGB

H/V

Defl.

✔✔✔✔

FIFO

VPC

32xx

CVBS

DDP

3310B

RGB

H/V

Defl.

✔✔

✔

VPC 32xxD

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