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MCP19124 bảng dữ liệu(PDF) 96 Page - Microchip Technology

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MCP19124/5
DS20005619A-page 96
 2016 Microchip Technology Inc.
13.3.1.3
PIR1 Register
The PIR1 register contains the Peripheral Interrupt
Flag bits, as shown in Register 13-4.
Note 1: Interrupt flag bits are set when an
interrupt condition occurs, regardless of
the state of its corresponding enable bit
or the Global Enable bit (GIE) in the
INTCON register. The user’s software
should ensure the appropriate interrupt
flag bits are clear prior to enabling an
interrupt.
REGISTER 13-4:
PIR1: PERIPHERAL INTERRUPT FLAG REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
BCLIF
SSPIF
CC2IF
CC1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’
= Bit is set
‘0’
= Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
BCLIF: MSSP Bus Collision Interrupt Flag bit
1
= Interrupt is pending
0
= Interrupt is not pending
bit 4
SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1
= Interrupt is pending
0
= Interrupt is not pending
bit 3
CC2IF: Capture2/Compare2 Interrupt Flag bit
1
= Capture or Compare has occurred
0
= Capture or Compare has not occurred
bit 2
CC1IF: Capture1/Compare1 Interrupt Flag bit
1
= Capture or Compare has occurred
0
= Capture or Compare has not occurred
bit 1
TMR2IF: Timer2 to PR2 Match Interrupt Flag
1
= Timer2 to PR2 match occurred (must be cleared in software)
0
= Timer2 to PR2 match did not occur
bit 0
TMR1IF: Timer1 Interrupt Flag
1
= Timer1 rolled over (must be cleared in software)
0
= Timer1 has not rolled over



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