PC87310 datasheet(42/52 Pages) NSC

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60 DC Electrical Characteristics

VDD e 5V g10% VSS e 0V unless otherwise specified (Note 3) (Continued)

Symbol

Parameter

Conditions

Min

Max

Units

MICROPROCESSOR AND PARALLEL PORT PINS

VOL

Output Low Voltage

IOL e 24 mA on D0–D7

IOL e 16 mA on PD0–PD7

IOL e 12 mA on All Other Outputs

VOH

Output High Voltage

IOH eb6mAonD0–D7

IOH eb6mAonPD0–PD7

IOH eb1 mA On INIT AFD STB and SLIN

(Note 5)

IOH eb02 mA on All Other Outputs

IIL

Input Leakage

VDD e 55V VSS e 0V

All Other Pins Floating

IOZ

Output TRI-STATE Leakage

VDD e 55V VSS e 0V

VOUT e 0V 55V

61 PHASE LOCKED LOOP CHARACTERISTICS

VCC e 5V g10% FXTAL e 24 MHz unless otherwise specified

Symbol

Parameter

Conditions

Typ

Units

VREF

SETCUR Pin Reference

R1 e 56 kX VCC e 5V

Voltage

KVCO

VCO Gain (Note 1)

tDATA e 1 ms g10%

MradsV

Recommended Pump

3–12

Resistor Range

KP(UP)

Charge Pump Up Current

R1 e 56 kX

250

(none)

Gain (IREF IP(UP)) (Note 2)

KP(DWN)

Charge Pump Down Current

R1 e 56 kX

225

(none)

Gain (IREF IP(DWN)) (Note 2)

KPLL

Internal Phase Locked Loop

(R1 e 56 kX)

Gain (Note 3)

Pump Up

Mrad

Pump Down

Mrad

TSW

Static Window

Early

Late

(Note 4)

(R1 e 56 kX)

250 kbs

1075

872

500 kbs

530

440

10 Mbs

259

234

TDW

Dynamic Window

(Note)

Margin

Note

Measurements made with a repeating ‘‘DB6’’ data pattern with reverse write precompensation using recommended filter values for the configuration shown

Figure 3c 25 C 50V 0% MSV

Note 1

The VCO gain is measured at the 10 Mbs data rate by forcing the data period over a range from 900 ns to 1100 ns and measuring the resulting voltage

on the filter pin The best straight line gain is fit to the measured points

Note 2

This is the current gain of the charge pump which is defined as the output current divided by the current through R1

Note 3

This is the product of VREF c KP c KVCO The total variation in this specification indicates the total loop gain variation contributed by the internal circuitry

The KVCO portion of this specification is measured at the 10 Mbs data rate by forcing the data period over a range of 900 ns to 1100 ns and measuring the

resultant KVCO KP is measured by forcing the Filter pin to 21V and measuring the ratio of the charge pump current over the input current

Note 4

The FDC is guaranteed to correctly decode a single shifted clock pulse at the end of a long series of non-shifted preamble bits as long as the single shifted

pulse is shifted less than the amount specified in TSW The length of the preamble is long enough for the PLL to lock The filter components used are those in

Table 4-8

Note 5

INIT AFD STB and SLIN are open collector output pins that require pull-up resistors (47 kX)toVDD

62 CAPACITANCE

TA e 25 C VDD e VSS e 0V

Symbol

Parameter

Conditions

Min

Typ

Max

Units

CIN

Input Capacitance

fc e 1 MHz

COUT

Output Capacitance

Unmeasured Pins

CIO

InputOutput Capacitance

Returned to VSS

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