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PC87310 bảng dữ liệu(PDF) 40 Page - National Semiconductor (TI) |
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PC87310 bảng dữ liệu(HTML) 40 Page - National Semiconductor (TI) |
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40 / 52 page ![]() 40 Functional Description (Continued) 47 GAME PORT 471 PC87310 Interface to the AT Game Port To interface with the game port all that is required is the logic shown in Figure 8 and the qualification of the read and write signals Since the PC87310 provides the game port chip select (GPEN pin 18) the game read and game write signals can be easily qualified by gating GPEN with IOR and IOW A typical game port circuit is shown below (The game port is implemented by using a 74LS244 buffer NE558 Quad Timer and some resistors and capacitors) 472 PC87310 Interface to the XT Game Port This interface is essentially the same as for the AT except that the game port read and write signals are qualified on the PC87310 These qualified read and write signals are provided from the PC87310 via the GRD and GWR signals directly This eliminates the need for 2 OR gates in the ex- ternal game port logic TLC10591 – 19 FIGURE 8 AT Game Port 40 |
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