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GL811USB bảng dữ liệu(PDF) 17 Page - List of Unclassifed Manufacturers

tên linh kiện GL811USB
Giải thích chi tiết về linh kiện  USB 2.0 to ATA / ATAPI Bridge Controller
PDF  36 Pages
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nhà sản xuất  ETC [List of Unclassifed Manufacturers]
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GL811USB bảng dữ liệu(HTML) 17 Page - List of Unclassifed Manufacturers

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GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller
©2000-2002 Genesys Logic Inc.—All rights reserved.
Page 16
3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is
released prior to negation and may be asserted for no more than 5 ns before release: no
wait generated.
3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be
asserted for no more than 5 ns before release: wait generated. The cycle completes after
IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the
device shall read data on IODD(0:7) for tRD before asserting IORDY.
4.DMACK_ shall remain negated during a register transfer.
Register transfer timing parameters
Timing (ns)
t0
Cycle time
2000
t1
Address valid to DIOR_/ DIOW_ setup
1000
t2
DIOR_/ DIOW_ pulse width 8-bit
300
t2i
DIOR_/ DIOW_ recovery time
900
t3
DIOW_ data setup
80
t4
DIOW_ data hold
40
t5
DIOR_ data setup
-
t6
DIOR_ data hold
-
t6Z
DIOR_ data tristate
-
t9
DIOR_/ DIOW_ to address valid hold
900
tRD
Read Data Valid to IORDY active
(if IORDY initially low after tA)
tA
IORDY Setup time
-
tB
IORDY Pulse Width
-
tC
IORDY assertion to release (max)
-



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