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GC2011A bảng dữ liệu(PDF) 34 Page - Texas Instruments |
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GC2011A bảng dữ liệu(HTML) 34 Page - Texas Instruments |
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34 / 50 page ![]() Texas Instruments Incorporated - 30 - GC2011A 3.3V DIGITAL FILTER CHIP SLWS129A This document contains information which may be changed at any time without notice The operation of these control bits are illustrated in the following figures. Figure 7. Input Timing NOTES: (1) The TC strobe appears 8 clocks after SI and every 16*(CNT+1) clocks thereafter. (2) The input delays selected by the DEL_SEL control are clock cycle delays, not sample delays. These delays occur before the input rate circuit captures the samples as shown above. Figure 8. Output Timing X0 X0 X0 X1 X2 X3 X1 012345 6789 CK TIME SI SO TC Full Rate Half Rate Quarter Rate even odd even odd even odd even (a) DEL_SEL = 0 (no delay) Full Rate Half Rate (b) DEL_SEL = 1 (1 clock delay) Full Rate Half Rate (c) DEL_SEL = 2 (3 clock delay) Quarter Rate Quarter Rate X1 odd X2 even X0 X0 X0 X1 X2 X3 X1 even odd even odd even odd even X1 odd X2 even X0 X0 X0 X1 X2 X3 X1 even odd even odd even odd even X1 odd X2 even X3 odd X3 odd X2 even 012345 6789 CK TIME SI Full Rate (ACCUM = 0,1, The DAV output is always high) Half Rate (ACCUM = 3) DAV Quarter Rate (ACCUM = 2) DAV even odd even odd even odd even even odd even odd even odd even odd odd odd even |
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