GC2011A datasheet(40/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

6.8

SNAPSHOT START CONTROL REGISTER

This register controls the snapshot trigger settings, the snapshot read modes and the chip’s sync modes.

ADDRESS 10:

SNAP_REGC

BIT

TYPE

NAME

DESCRIPTION

0,1 (LSBs)

R/W

TRIGGER

This control sets the trigger condition which will start a snapshot once

the ARMED bit is set. The trigger conditions are to start:

TRIGGER

DESCRIPTION

immediately,

when the SN strobe is received,

when the SI strobe is received,

when the TC strobe is received.

2,3

R/W

READ_MODE

Selects whether words or bytes are read from the snapshot memory

according to:

READ_MODE

DESCRIPTION

0,2

read words,

read the least significant bytes

read the most significant bytes

When reading bytes, the bytes are placed in the LSBs of the 16 bit

control word and sign extended.

R/W

ARMED

The user sets this bit to arm the snapshot memory so that it will

start on the next trigger condition. The chip clears this bit when

the trigger occurs.

R/W

A_DONE

This bit goes high when the A-half snapshot is complete. This bit

must be cleared by writing a zero to it.

R/W

B_DONE

This bit goes high when the B-half snapshot is complete. This bit

must be cleared by writing a zero to it.

R/W

unused

8,9

R/W

SYNC_OUT

This two bit field selects the sync output (SO) source as:

SYNC_OUT

DESCRIPTION

SI delayed by 4 clocks (SYNC_OFF=0),

TC,

OS,

never

R/W

SYNC_OFF

This bit disables the sync input to the chip. The counter will free

run when this bit is high

11-15

R/W

unused

6.9

ONE SHOT ADDRESS

The one shot pulse is generated on the OS pin by writing to address 11. This is a write-only address. The data

written to it is irrelevant.

ADDRESS 11:

ONE_SHOT

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