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MT9072AB bảng dữ liệu(PDF) 242 Page - Zarlink Semiconductor Inc

tên linh kiện MT9072AB
Giải thích chi tiết về linh kiện  Octal T1/E1/J1 Framer
PDF  275 Pages
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nhà sản xuất  ZARLINK [Zarlink Semiconductor Inc]
Trang chủ  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB bảng dữ liệu(HTML) 242 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
242
Zarlink Semiconductor Inc.
* Timing for output signals is based on the worst case result of the combination of TTL and CMOS thresholds.
Figure 27 - Timing Parameter Measurement Voltage Levels
‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1. High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels* - Voltages are with respect to
ground (VSS) unless otherwise stated.
Characteristics
Sym.
Level
Units
Conditions/Notes
1
Threshold Voltage
VT
1.5
0.5
∗V
DD
V
V
TTL
CMOS
2
Rise/Fall Threshold Voltage High
VHM
2.0
0.7
∗V
DD
V
V
TTL
CMOS
3
Rise/Fall Threshold Voltage Low
VLM
0.8
0.3
∗V
DD
V
V
TTL
CMOS
AC Electrical Characteristics - Motorola Microprocessor Timing*
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
1DS low
tDSL
115
ns
2DS High
tDSH
50
ns
3CS Setup
tCSS
0ns
4CS Hold
tCSH
0ns
5R/W Setup
tRWS
15
ns
6R/W Hold
tRWH
0ns
7
Address Setup
tADS
15
ns
8
Address Hold
tADH
40
ns
9
Data Delay Read
tDDR
100
ns
CL = 150 pF, RL = 1 kΩ
10
Data Hold Read
tDHR
5ns
CL = 150 pF, RL = 1 kΩ
11
Data Active to High Z Delay
tDAZ
50
ns
CL = 150 pF, RL = 1 kΩ,
Note 1
12
Data Setup Write
tDSW
15
ns
13
Data Hold Write
tDHW
25
ns
14
Cycle Time
tCYC
165
ns
ALL SIGNALS
tIRF, tORF
Timing Reference Points
VT
VHM
VLM
tIRF, tORF



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