MT9072AB datasheet(153/275 Pages) ZARLINK

153 / 275 page

MT9072

Data Sheet

153

Zarlink Semiconductor Inc.

8F6SM

(0)

Framer 6 Sync and Overflow Mask. This is the mask bit for the F6SVS status bit in the Interrupt

Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit

will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

7F5HM

(0)

Framer 5 HDLC Mask. This is the mask bit for the F5HVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

6F5EM

(0)

Framer 5 Elastic Mask. This is the mask bit for the F5EVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

5F5RM

(0)

Framer 5 Rx Line Mask. This is the mask bit for the F5RVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

4F5SM

(0)

Framer 5 Sync and Overflow Mask. This is the mask bit for the F5SVS status bit in the Interrupt

Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit

will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

3F4HM

(0)

Framer 4 HDLC Mask. This is the mask bit for the F5HVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

2F4EM

(0)

Framer 4 Elastic Mask. This is the mask bit for the F4EVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

1F4RM

(0)

Framer 4 Rx Line Mask. This is the mask bit for the F4RVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

0F4SM

(0)

Framer 4 Sync and Overflow Mask. This is the mask bit for the F4SVS status bit in the Interrupt

Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit

will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

Bit

Name

Functional Description

Table 122 - Interrupt Vector 2 Mask Register (Address 903) (T1)

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