MT9072AB datasheet(104/275 Pages) ZARLINK

104 / 275 page

MT9072

Data Sheet

104

Zarlink Semiconductor Inc.

16.0

JTAG (Joint Test Action Group) Operation

The MT9072 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-1990.

This standard specifies a design-for-testability technique called Boundary-Scan test (BST). Figure 10 shows the

BST architecture which is made up of the following four basic elements. See Figure 30 for JTAG timing.

1. Test Access Port (TAP)

2. TAP Controller

3. Instruction Register (IR)

4. Test Data Registers (TDR)

Figure 10 - Boundary Scan Test Circuit Block Diagram

16.1

Test Access Port (TAP)

The Test Access Port (TAP) provides access to the many test functions of the MT9072. It consists of four input pins

and one output pin. The following pins are from the TAP.

Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK signal does not interfere with any

on-chip clocks and thus remains independent. The TCK permits shifting of test data into or out of the

Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip

logic.

Test Mode Select Input (TMS) - The logic signals received at the TMS input are interpreted by the TAP Controller

to control the test operations. The TMS signal is sampled at the rising edge of the TCK pulses. This pin is internally

pulled up to device VDD when it is not driven from an external source.

TDI

TDO

TMS

TCK

TRST

TAP

Instruction Register

Bypass Register

Device ID Register

Test Data Registers

Framer

Input

Pins

Framer

Output

Pins

Framer

Core

Logic

Boundary Scan

TAP

Controller

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