AS4C32M16D2 datasheet(49/70 Pages) ALSC

49 / 70 page

AS4C32M16D2

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL: (650) 610-6800

FAX: (650) 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

Rev. 1.1

Feb. /2013

Figure 23. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8)

CK#

CMD

Read A

NOP

Read B

NOP

DQS

DQS#

DQs

NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write

command or Precharge command is prohibited.

NOTE 3: Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst

interrupt timings are prohibited.

NOTE 4: Read burst interruption is allowed to any bank inside DRAM.

NOTE 5: Read burst with Auto Precharge enabled is not allowed to interrupt.

NOTE 6: Read burst interruption is allowed by another Read with Auto Precharge command.

NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to

actual burst. For example, Minimum Read to Precharge timing is AL+BL/2 where BL is the burst length set in the

mode register and not the actual burst (which is shorter because of interrupt).

Figure 24. Data input (write) timing

DQS#

DQS

tDQSH

tWPRE

DQS

tDQSL

tWPSL

VIL(ac)

VIH(ac)

VIL(dc)

VIH(dc)

DMin

DQS#

DMin

VIH(ac)

VIL(ac)

DMin

VIH(dc)

VIL(dc)

tDS

tDH

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