AS4C32M16D2 datasheet(32/70 Pages) ALSC

32 / 70 page

AS4C32M16D2

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL: (650) 610-6800

FAX: (650) 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

Rev. 1.1

Feb. /2013

Figure 7. Slew rate test load

VDDQ

DUT DQS

DQS#

VTT=VDDQ/2

25Ω

Test point

Ouput

NOTE 4: Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the

setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The

method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing

relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these

timing relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This distinction in

timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is

disabled via the EMRS, the complementary pin, DQS#, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor

to insure proper operation

NOTE 5: AC timings are for linear signal transitions.

NOTE 6: All voltages are referenced to VSS.

NOTE 7: These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be

guaranteed by device design or tester correlation.

NOTE 8:

Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal

reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full

voltage range specified.

Specific notes for dedicated AC parameters

NOTE 1: User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for

fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing where a

lower power value is defined by each vendor data sheet.

NOTE 2: AL=Additive Latency.

NOTE 3: This is a minimum requirement. Minimum read to precharge timing is AL+BL/2 provided that the tRTP and tRAS

(min) have been satisfied.

NOTE 4: A minimum of two clocks (2* tCK) is required irrespective of operating frequency.

NOTE 5: Timings are specified with command/address input slew rate of 1.0 V/ns.

NOTE 6: Timings are specified with DQs, DM, and DQS’s (in single ended mode) input slew rate of 1.0V/ns.

NOTE 7: Timings are specified with CK/CK# differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals

with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode.

AS4C32M16D2 bảng dữ liệu(PDF) 32 Page - Alliance Semiconductor Corporation

AS4C32M16D2 bảng dữ liệu(HTML) 32 Page - Alliance Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

bảng dữ liệu tải về

Link URL