AR0141CS datasheet(21/64 Pages) ONSEMI

21 / 64 page

AR0141CS/D Rev. 6, 4/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0141CS: 1/4-Inch Digital Image Sensor

Sensor PLL

Serial PLL Configuration

Figure 20:

PLL for the Serial Interface

The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per

lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4)

configured. To configure the sensor protocol and number of lanes, refer to “Serial

Configuration” on page 16.

Configure the serial output so that it adheres to the following rules:

• The maximum data-rate per lane (FSERIAL) is 600Mbps/lane (HiSPi).

• Configure the output pixel rate per lane (CLK_OP) so that the sensor output pixel rate

matches the peak pixel rate (2 x CLK_PIX).

– 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 148.5 Mpixel/s)

– 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 74.25 Mpixel/s)

Table 8:

PLL Parameters for the Serial Interface

Parameter

Symbol

Min

Max

Unit

External Clock

EXTCLK

MHz

VCO Clock

FVCO

384

768

MHz

Readout Clock

CLK_PIX

74.25

Mpixel/s

Output Serial Data Rate Per Lane

FSERIAL

300 (HiSPi)

600 (HiSPi)

Mbps

Output Serial Clock Speed Per Lane

FSERIAL_CLK

150 (HiSPi)

350(HiSPi)

MHz

Table 9:

Example PLL Configurations for the Serial Interface

Parameter

4-lane

2-lane

Units

12-bit

FVCO

445.5

MHz

vt_sys_clk_div

vt_pix_clk_div

op_sys_clk_div

F SERIAL

F VCO

CLK_PIX

CLK_OP

EXTCLK

(6-50 MHz)

F SERIAL_CLK

1/2

pre_pll_clk_div

2 (1-64)

vt_pix_clk_div

6 (4-16)

vt_sys_clk_div

1 (1, 2, 4, 6, 8,

10, 12, 14, 16)

pll_multiplier

58 (32-384)

op_sys_clk_div

(default = 1)

op_pix_clk_div

12 (8, 10, 12, 14, 16)

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