AR0141CS datasheet(13/64 Pages) ONSEMI

13 / 64 page

AR0141CS/D Rev. 6, 4/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0141CS: 1/4-Inch Digital Image Sensor

Pixel Output Interfaces

High Speed Serial Pixel Data Interface

The High Speed Serial Pixel (HiSPi) interface uses four data lanes and one clock as

output.

•SLVSC_P

•SLVSC_N

•SLVS0_P

•SLVS0_N

•SLVS1_P

•SLVS1_N

•SLVS2_P

•SLVS2_N

•SLVS3_P

•SLVS3_N

The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized

SP. The streaming protocols conform to a standard video application where each line of

active or intra-frame blanking provided by the sensor is transmitted at the same length.

The Packetized SP protocol will transmit only the active data ignoring line-to-line and

frame-to-frame blanking data.

These protocols are further described in the High-Speed Serial Pixel (HiSPi) Interface

Protocol Specification V1.50.00.

The HiSPi interface building block is a unidirectional differential serial interface with

four data and one double data rate (DDR) clock lanes. One clock for every four serial

data lanes is provided for phase alignment across multiple lanes. Figure 9 shows the

configuration between the HiSPi transmitter and the receiver.

Figure 9:

HiSPi Transmitter and Receiver Interface Block Diagram

A camera containing

the HiSPi transmitter

A host (DSP) containing

the HiSPi receiver

Dp0

Dn0

Dp1

Dn1

Dp2

Dn2

Dp3

Dn3

Cp0

Cn0

PHY0

Dp0

Dn0

Dp1

Dn1

Dp2

Dn2

Dp3

Dn3

Cp0

Cn0

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