AR0141CS datasheet(19/64 Pages) ONSEMI

19 / 64 page

AR0141CS/D Rev. 6, 4/16 EN

©Semiconductor Components Industries, LLC, 2016.

AR0141CS: 1/4-Inch Digital Image Sensor

Data Pedestals

The data pedestal is a constant offset that is added to pixel values at the end of the data-

path. The default offset is 168 and is a 12-bit offset. This offset matches the maximum

range used by the corrections in the digital readout path. The purpose of the data

pedestal is to convert negative values generated by the digital datapath into positive

output data.

Reset

The AR0141CS may be reset by the RESET_BAR pin (active LOW) or the reset register.

Hard Reset of Logic

The host system can reset the image sensor by bringing the RESET_BAR pin to a LOW

state. Alternatively, the RESET_BAR pin can be connected to an external RC circuit for

simplicity. Registers written via the two-wire interface will not be preserved following a

hard reset.

Soft Reset of Logic

Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the

digital logic of the sensor. Furthermore, by asserting the soft reset, the sensor aborts the

current frame it is processing and starts a new frame. This bit is a self-resetting bit and

also returns to “0” during two-wire serial interface reads.

Clocks

The AR0141CS requires one clock input (EXTCLK).

Sensor PLL

VCO

Figure 18:

PLL Dividers Affecting VCO Frequency

The sensor contains a phase-locked loop (PLL) that is used for timing generation and

control. The required VCO clock frequency is attained through the use of a pre-PLL clock

divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd

integer (M) is programmed, the PLL will default to the lower (M-1) value to maintain an

even multiplier value. The multiplier is followed by a set of dividers used to generate the

output clocks required for the sensor array, the pixel analog and digital readout paths,

and the output parallel and serial interfaces.

EXTCLK

(6-50 MHz)

pre_pll_clk_div

2 (1-64)

pll_multiplier

58 (32-384)

VCO

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