AP0100CS datasheet(50/73 Pages) ONSEMI

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AP0100CS HDR: Image Signal Processor (ISP)

Host Command Interface

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

Host Command Interface

The AP0100CS has a mechanism to write higher level commands, the Host Command

Interface (HCI). Once a command has been written through the HCI, it will be executed

by on chip firmware and the results are reported back. EEPROM or Flash memory is also

available to store commands for later execution.

Figure 38:

Interface Structure

Command Flow

The host issues a command by writing (through the two wire interface) to the Command

‘host command’ (doorbell) interrupt to the microprocessor.

Assuming initial conditions, the host first writes the command parameters (if any) to the

Parameters Pool (in the Command Handler’s shared-variable page), then writes the

command to Command Register. The firmware’s interrupt handler is invoked, which

immediately copies the Command Register contents. The interrupt handler then signals

the Command Handler task to process the command.

Host Command to FW

Response from FW

bit

command register

Addr 0x40

Addr 0xFC00

Addr 0xFC0E

Addr 0xFC02

Addr 0xFC04

Addr 0xFC06

Addr 0xFC08

Addr 0xFC0A

Addr 0xFC0C

door bell

bit

Parameter 0

Parameter 7

cmd_handler_params_pool_0

cmd_handler_params_pool_1

cmd_handler_params_pool_2

cmd_handler_params_pool_3

cmd_handler_params_pool_4

cmd_handler_params_pool_5

cmd_handler_params_pool_6

cmd_handler_params_pool_7

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